Common problems in PCB design
1. How to name the inner layer for 4-layer PCB? Here is the better naming as following.
G1/Inner1------the second layer;
G2/Inner2------the third layer
Sometime we find the inner layer named “ly2”, “ly15” or “GND”, “Power”, that make us feel puzzle for we are not sure which is the second layer or the third layer.
2. My PCB just has 3-layer and one inner layer is empty, could I choose 4-layer PCB for it?
That is OK to choose 4-layer PCB for it.
3. What is the inner copper weight of 1oz and 2oz 4-layer, 6-layer and 8-layer PCB?
For multilayer board with 1oz outer copper, inner copper is 0.5oz. If outer copper is 2oz, inner one is 1oz.
4. Can you make the holes and characters which are in Paste Layer in the stencil?
We skip through-hole component pads and all drills (holes) by default except the fiducial, so you need to leave a message to us if you want to make the holes of the GTP and GBP. Besides, we couldn’t make the characters in the stencil.
5. There is no need to make the board with solder mask, just exposed copper for the whole panel, what should I do?
Please don’t put the solder mask layer in your gerber or keep the solder mask layer empty. Or make the solder mask layer full with exposed copper in your gerber.
6. I don’t want to make silkscreen for my PCB, could I leave the silkscreen empty?
That would be better to leave the silkscreen empty.
7.Is there a way to provide the information regarding non-plated through holes to you in future designs?
We will plate all the holes by default. If you need some holes not be plated, please name the plated holes/via layer as PCBname-PHT.txt and name the non-plated holes layer as PCBname- NPTH.txt.
PS: For holes display on the GML/GKO layer, we will fabricate it as Non-plated default. If it need to fabricate as plated holes.
8. How to deal with some theoretical conflicts in PCB layout
① Basically, it is right to divide and isolate analog / digital. It should be noted that the signal should not cross the moat as far as possible, and the return current path of power supply and signal should not be too large.
② Crystal oscillator is an analog positive feedback oscillation circuit. In order to have a stable oscillation signal, it must meet the specifications of loop gain and phase, and the oscillation specifications of the analog signal are easy to be interfered, even if the ground guard traces are added, the interference may not be completely isolated. Moreover, if it is too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. So, be sure to keep the distance between the crystal oscillator and the chip as close as possible.
③ It is true that there are many conflicts between high-speed wiring and EMI requirements. But the basic principle is that some electrical characteristics of the signal can not meet the specification because of the resistance and capacitance or ferrite beam added by EMI. Therefore, it's better to use the technique of routing and PCB stacking to solve or reduce the EMI problem, such as high-speed signal going to the inner layer. Finally, resistance and capacitance or ferrite bead are used to reduce the damage to the signal.
9. Why should the layout of differential pairs be close and parallel?
The layout of differential pairs should be close and parallel. The appropriate approach is because the distance will affect the value of differential impedance, which is an important parameter in the design of differential pairs. The need for parallelism is also due to the consistency of the differential impedance. If the two lines are far or near, the differential impedance will be inconsistent, which will affect the signal integrity and timing delay.